Date:	July 24th, 2024 (Wednesday)
Time:	16:30-18:30
Venue:	Hong Kong Science & Technology Park

The following Tutorial from Avnet is offered to all registered delegates of ASAP 2024:

Introduction
The Versal® ACAP is a fully software programmable, heterogeneous compute platform that combines the following:

• Scalar Engines (a processor subsystem (PS) that includes Arm® processors)
• Adaptable Engines (programmable logic (PL) and memory)
• Intelligent Engines (including both including both AI and DSP Engines)

This tutorial performs two implementations of a system-level design: one with AI Engine, and the other with HLS using the DSP Engines. In each implementation, the tutorial takes you through the hardware emulation and hardware flow in the context of a complete Versal ACAP system design.

Objectives
After completing the tutorial, you should be able to:

• Develop a system-level 2D-FFT design by identifying an algorithm and deploying it on AI Engines or PL and DSP Engines using Vitis™ HLS.
• Build a complete system design by going through the following steps in the Vitis flow:
• Create the AI Engine Adaptive Data Flow API (ADF) graph.
• Compile the A72 host application and compiling PL kernels.
• Use the Vitis compiler (V++) to link the AI Engine and HLS kernels with the platform.
• Package the design.
• Run the design through the hardware emulation and hardware flow in a mixed SystemC/RTL cycle-accurate/QEMU-based simulator.
• Develop a consistent harness to have the data mover kernels maintain a similar interface with AI Engine or HLS/PL kernels (using AXI4-Stream)

Participants please bring a fully-charged laptop to the tutorial session.